I think the problem is that processors can have slightly different instruction sets, possibly less likely with ARM and RISC (Reduced Instruction, after all), and how they interpret bits and jumps (big endian, low endian). Chibi Akumas has a lot of material for learning assembly of various CPUs, including older ones like 68k and 6502, something I’m doing on and off once in a while
I think the problem is that processors can have slightly different instruction sets, possibly less likely with ARM and RISC (Reduced Instruction, after all), and how they interpret bits and jumps (big endian, low endian). Chibi Akumas has a lot of material for learning assembly of various CPUs, including older ones like 68k and 6502, something I’m doing on and off once in a while
Solution: everyone speaks in some form of IR.
So, brainfuck assembly?